The Resource Advances in 3D integrated circuits and systems, Hao Yu (NTU, Singapore), Chuan-Seng Tan (NTU, Singapore)

Advances in 3D integrated circuits and systems, Hao Yu (NTU, Singapore), Chuan-Seng Tan (NTU, Singapore)

Label
Advances in 3D integrated circuits and systems
Title
Advances in 3D integrated circuits and systems
Statement of responsibility
Hao Yu (NTU, Singapore), Chuan-Seng Tan (NTU, Singapore)
Creator
Contributor
Author
Subject
Genre
Language
  • eng
  • eng
Summary
"3D integration is an emerging technology for the design of many-core microprocessors and memory integration. This book, Advances in 3D Integrated Circuits and Systems, is written to help readers understand 3D integrated circuits in three stages: device basics, system level management, and real designs. Contents presented in this book include fabrication techniques for 3D TSV and 2.5D TSI; device modeling; physical designs; thermal, power and I/O management; and 3D designs of sensors, I/Os, multi-core processors, and memory. Advanced undergraduates, graduate students, researchers and engineers may find this text useful for understanding the many challenges faced in the development and building of 3D integrated circuits and systems."--
Assigning source
Provided by publisher
Cataloging source
MiAaPQ
http://library.link/vocab/creatorName
Yu, Hao
Dewey number
621.3815
Illustrations
  • illustrations
  • charts
Index
index present
Language note
English
LC call number
TK7874.893
LC item number
.Y83 2016
Literary form
non fiction
Nature of contents
  • dictionaries
  • bibliography
http://library.link/vocab/relatedWorkOrContributorName
Tan, Chuan Seng
Series statement
Series on emerging technologies in circuits and systems
Series volume
volume 1
http://library.link/vocab/subjectName
Three-dimensional integrated circuits
Label
Advances in 3D integrated circuits and systems, Hao Yu (NTU, Singapore), Chuan-Seng Tan (NTU, Singapore)
Instantiates
Publication
Copyright
Note
Description based upon print version of record
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
cr
Content category
text
Content type code
txt
Contents
  • Contents; Preface; 1. Introduction; 1.1 Thousand-core On-chip; 1.2 State-of-the-Art Many-core Microprocessors; 1.3 Memory-logic Integration; 1.3.1 2D Integration Challenges; 1.3.1.1 Scalability; 1.3.1.2 Channel Loss; 1.3.1.3 I/O Circuit Design; 1.3.1.4 Testing; 1.3.1.5 Thermal Management; 1.3.1.6 Power Management; 1.3.1.7 I/OManagement; 1.3.2 3D Integration; 1.3.3 2.5D Integration; 1.4 Organization of the Book; Part 1. Device Modeling; 2. Fabrication; 2.1 Introduction; 2.2 TSV Structure and Fabrication; 2.2.1 Structure Design; 2.2.1.1 Wafer Layout and Mask Design
  • 2.2.1.2 Electrical Structure Design2.2.1.3 Thermal Structure Design; 2.2.1.4 Dummy TSV Blocks; 2.2.2 Fabrication Process; 2.2.2.1 Electrical Structure Fabrication Process; 2.2.2.2 Thermal Structure Fabrication Process; 2.2.3 Process Control and Optimization; 2.2.3.1 DRIE Si Etch; 2.2.3.2 Dielectric Liner Deposition; 2.2.3.3 Ta Barrier/Cu Seed Layer Deposition and Cu ECP; 2.2.3.4 Cu CMP; 2.3 TSV Electrical Characterization; 2.3.1 Measurement Setup; 2.3.2 Conventional PETEOS Oxide Liner; 2.3.2.1 Electrical CV Measurement; 2.3.2.2 Electrical IV Measurement; 2.3.3 Black Diamond Low-k Liner
  • 2.3.3.1 Electrical CV Measurement2.3.3.2 Electrical IV Measurement; 2.3.4 Al2O3/Oxide Bi-layer Liner; 2.3.4.1 Electrical CV Measurement; 2.3.4.2 Electrical IV Measurement; 2.4 TSV Thermal Characterization Results; 2.4.1 Measurement Setup; 2.4.2 Cu-TSV Thermal Modeling; 2.4.3 Cu-TSV Induced Stress Modeling; 2.4.4 Cu-TSV Induced Stress Measurement by Micro-Raman Analysis; 2.5 TSI Structure and Fabrication; 2.5.1 Structure Design; 2.5.2 Fabrication Process; 2.6 Summary; 3. Device Model; 3.1 Introduction; 3.2 Nonlinear MOSCAP Model; 3.3 TSV Device Model; 3.3.1 Electrical Model
  • 3.3.2 Thermal Model3.3.3 Mechanical Model; 3.3.4 Delay Model; 3.3.4.1 Electrical-Thermal Coupled Delay Model; 3.3.4.2 Electrical-Mechanical Coupled Delay Model ; 3.3.4.3 Electrical-Thermal-Mechanical Coupled Delay Model; 3.3.5 Power Model; 3.4 TSI Device Model; 3.4.1 Delay Model; 3.4.1.1 T-line Model; 3.4.1.2 Delay of T-line; 3.4.2 Power Model; 3.4.2.1 TSV and TSI Comparison; 3.4.2.2 Energy-efficiency Analysis; 3.5 Summary; Part 2. Physical Design; 4. Macromodel; 4.1 Introduction; 4.2 Power and Thermal Integrity; 4.3 Macromodeling; 4.3.1 Complexity Compression
  • 4.3.1.1 Complexity Compression of States4.3.1.2 Complexity Compression of I/Os; 4.3.2 Parameterization; 4.4 Summary; 5. TSV Allocation; 5.1 Introduction; 5.2 Power Ground Design; 5.2.1 Problem Formulation; 5.2.2 Sensitivity based TSV Allocation; 5.3 Clock-treeDesign; 5.3.1 ProblemFormulation; 5.3.2 Sensitivity based TSV Allocation; 5.3.2.1 Reduction of Thermal Gradient; 5.3.2.2 Reduction of Stress Gradient; 5.3.2.3 Clock-skew Reduction; 5.4 Summary; 6. Testing; 6.1 Introduction; 6.2 3D IC Test; 6.2.1 System Architecture; 6.2.2 Problem Formulation
  • 6.3 Compressive Sensing and Recovery of Testing Data
Dimensions
unknown
Extent
1 online resource (392 p.)
Form of item
online
Isbn
9789814699020
Media category
computer
Media type code
c
Specific material designation
remote
System control number
  • (CKB)3710000000482344
  • (EBL)4394880
  • (SSID)ssj0001552629
  • (PQKBManifestationID)16171264
  • (PQKBTitleCode)TC0001552629
  • (PQKBWorkID)14076053
  • (PQKB)11703955
  • (MiAaPQ)EBC4394880
  • (WSP)00009672
  • (EXLCZ)993710000000482344
Label
Advances in 3D integrated circuits and systems, Hao Yu (NTU, Singapore), Chuan-Seng Tan (NTU, Singapore)
Publication
Copyright
Note
Description based upon print version of record
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
cr
Content category
text
Content type code
txt
Contents
  • Contents; Preface; 1. Introduction; 1.1 Thousand-core On-chip; 1.2 State-of-the-Art Many-core Microprocessors; 1.3 Memory-logic Integration; 1.3.1 2D Integration Challenges; 1.3.1.1 Scalability; 1.3.1.2 Channel Loss; 1.3.1.3 I/O Circuit Design; 1.3.1.4 Testing; 1.3.1.5 Thermal Management; 1.3.1.6 Power Management; 1.3.1.7 I/OManagement; 1.3.2 3D Integration; 1.3.3 2.5D Integration; 1.4 Organization of the Book; Part 1. Device Modeling; 2. Fabrication; 2.1 Introduction; 2.2 TSV Structure and Fabrication; 2.2.1 Structure Design; 2.2.1.1 Wafer Layout and Mask Design
  • 2.2.1.2 Electrical Structure Design2.2.1.3 Thermal Structure Design; 2.2.1.4 Dummy TSV Blocks; 2.2.2 Fabrication Process; 2.2.2.1 Electrical Structure Fabrication Process; 2.2.2.2 Thermal Structure Fabrication Process; 2.2.3 Process Control and Optimization; 2.2.3.1 DRIE Si Etch; 2.2.3.2 Dielectric Liner Deposition; 2.2.3.3 Ta Barrier/Cu Seed Layer Deposition and Cu ECP; 2.2.3.4 Cu CMP; 2.3 TSV Electrical Characterization; 2.3.1 Measurement Setup; 2.3.2 Conventional PETEOS Oxide Liner; 2.3.2.1 Electrical CV Measurement; 2.3.2.2 Electrical IV Measurement; 2.3.3 Black Diamond Low-k Liner
  • 2.3.3.1 Electrical CV Measurement2.3.3.2 Electrical IV Measurement; 2.3.4 Al2O3/Oxide Bi-layer Liner; 2.3.4.1 Electrical CV Measurement; 2.3.4.2 Electrical IV Measurement; 2.4 TSV Thermal Characterization Results; 2.4.1 Measurement Setup; 2.4.2 Cu-TSV Thermal Modeling; 2.4.3 Cu-TSV Induced Stress Modeling; 2.4.4 Cu-TSV Induced Stress Measurement by Micro-Raman Analysis; 2.5 TSI Structure and Fabrication; 2.5.1 Structure Design; 2.5.2 Fabrication Process; 2.6 Summary; 3. Device Model; 3.1 Introduction; 3.2 Nonlinear MOSCAP Model; 3.3 TSV Device Model; 3.3.1 Electrical Model
  • 3.3.2 Thermal Model3.3.3 Mechanical Model; 3.3.4 Delay Model; 3.3.4.1 Electrical-Thermal Coupled Delay Model; 3.3.4.2 Electrical-Mechanical Coupled Delay Model ; 3.3.4.3 Electrical-Thermal-Mechanical Coupled Delay Model; 3.3.5 Power Model; 3.4 TSI Device Model; 3.4.1 Delay Model; 3.4.1.1 T-line Model; 3.4.1.2 Delay of T-line; 3.4.2 Power Model; 3.4.2.1 TSV and TSI Comparison; 3.4.2.2 Energy-efficiency Analysis; 3.5 Summary; Part 2. Physical Design; 4. Macromodel; 4.1 Introduction; 4.2 Power and Thermal Integrity; 4.3 Macromodeling; 4.3.1 Complexity Compression
  • 4.3.1.1 Complexity Compression of States4.3.1.2 Complexity Compression of I/Os; 4.3.2 Parameterization; 4.4 Summary; 5. TSV Allocation; 5.1 Introduction; 5.2 Power Ground Design; 5.2.1 Problem Formulation; 5.2.2 Sensitivity based TSV Allocation; 5.3 Clock-treeDesign; 5.3.1 ProblemFormulation; 5.3.2 Sensitivity based TSV Allocation; 5.3.2.1 Reduction of Thermal Gradient; 5.3.2.2 Reduction of Stress Gradient; 5.3.2.3 Clock-skew Reduction; 5.4 Summary; 6. Testing; 6.1 Introduction; 6.2 3D IC Test; 6.2.1 System Architecture; 6.2.2 Problem Formulation
  • 6.3 Compressive Sensing and Recovery of Testing Data
Dimensions
unknown
Extent
1 online resource (392 p.)
Form of item
online
Isbn
9789814699020
Media category
computer
Media type code
c
Specific material designation
remote
System control number
  • (CKB)3710000000482344
  • (EBL)4394880
  • (SSID)ssj0001552629
  • (PQKBManifestationID)16171264
  • (PQKBTitleCode)TC0001552629
  • (PQKBWorkID)14076053
  • (PQKB)11703955
  • (MiAaPQ)EBC4394880
  • (WSP)00009672
  • (EXLCZ)993710000000482344

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