The Resource Reconfigurable Computing: Architectures, Tools and Applications : 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings, edited by Roger Woods, Katherine Compton, Christos Bouganis, Pedro C. Diniz, (electronic resource)

Reconfigurable Computing: Architectures, Tools and Applications : 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings, edited by Roger Woods, Katherine Compton, Christos Bouganis, Pedro C. Diniz, (electronic resource)

Label
Reconfigurable Computing: Architectures, Tools and Applications : 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings
Title
Reconfigurable Computing: Architectures, Tools and Applications
Title remainder
4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings
Statement of responsibility
edited by Roger Woods, Katherine Compton, Christos Bouganis, Pedro C. Diniz
Creator
Contributor
Editor
Editor
Subject
Language
  • eng
  • eng
Member of
Is Subseries of
http://bibfra.me/vocab/relation/corporateauthor
NeuPGEmRElE
Dewey number
621.39/5
http://bibfra.me/vocab/relation/httpidlocgovvocabularyrelatorsedt
  • WERBP-euq-g
  • 2qWu-MhE1eE
  • 7PsrTlUkfiY
  • xHXmBdy3wiY
Image bit depth
0
Language note
English
LC call number
QA75.5-76.95
Literary form
non fiction
http://bibfra.me/vocab/lite/meetingDate
2008
http://bibfra.me/vocab/lite/meetingName
ARC 2008
Nature of contents
dictionaries
http://bibfra.me/vocab/lite/organizationName
ARC (Symposium)
http://library.link/vocab/relatedWorkOrContributorName
  • ARC (Symposium)
  • Woods, Roger.
  • Compton, Katherine.
  • Bouganis, Christos.
  • Diniz, Pedro C.
Series statement
Theoretical Computer Science and General Issues
Series volume
4943
http://library.link/vocab/subjectName
  • Information theory
  • Computer hardware
  • Computer science
  • Computer Communication Networks
  • Computer system performance
  • Computer network architectures
  • Theory of Computation
  • Computer Hardware
  • Processor Architectures
  • Computer Communication Networks
  • System Performance and Evaluation
  • Computer System Implementation
Label
Reconfigurable Computing: Architectures, Tools and Applications : 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings, edited by Roger Woods, Katherine Compton, Christos Bouganis, Pedro C. Diniz, (electronic resource)
Instantiates
Publication
Note
Bibliographic Level Mode of Issuance: Monograph
Antecedent source
mixed
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
cr
Color
not applicable
Content category
text
Content type code
txt
Contents
Keynotes -- Synthesizing FPGA Circuits from Parallel Programs -- From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing -- The von Neumann Syndrome and the CS Education Dilemma -- Programming and Compilation -- Optimal Unroll Factor for Reconfigurable Architectures -- Programming Reconfigurable Decoupled Application Control Accelerator for Mobile Systems -- DNA and String Processing Applications -- DNA Physical Mapping on a Reconfigurable Platform -- Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension -- Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs -- Scientific Applications -- A Custom Processor for a TDMA Solver in a CFD Application -- A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation -- Reconfigurable Computing Hardware and Systems -- Physical Design of FPGA Interconnect to Prevent Information Leakage -- Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs -- Run-Time Adaptable Architectures for Heterogeneous Behavior Embedded Systems -- Image Processing -- FPGA-Based Real-Time Super-Resolution on an Adaptive Image Sensor -- A Parallel Hardware Architecture for Image Feature Detection -- Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System -- Run-Time Behavior -- A New Self-managing Hardware Design Approach for FPGA-Based Reconfigurable Systems -- A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor -- Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens -- Instruction Set Extension -- ARISE Machines: Extending Processors with Hybrid Accelerators -- The Instruction-Set Extension Problem: A Survey -- Random Number Generation and Financial Computation -- An FPGA Run-Time Parameterisable Log-Normal Random Number Generator -- Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA -- Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models -- Posters -- Hybrid-Mode Floating-Point FPGA CORDIC Co-processor -- Multiplier-Based Double Precision Floating Point Divider According to the IEEE-754 Standard -- Creating the World’s Largest Reconfigurable Supercomputing System Based on the Scalable SGI® Altix® 4700 System Infrastructure and Benchmarking Life-Science Applications -- Highly Efficient Structure of 64-Bit Exponential Function Implemented in FPGAs -- A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures -- PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications -- Stream Transfer Balancing Scheme Utilizing Multi-path Routing in Networks on Chip -- Efficiency of Dynamic Reconfigurable Datapath Extensions – A Case Study -- Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices -- Data Reallocation by Exploiting FPGA Configuration Mechanisms -- A Networked, Lightweight and Partially Reconfigurable Platform -- Neuromolecularware – A Bio-inspired Evolvable Hardware and Its Application to Medical Diagnosis -- An FPGA Configuration Scheme for Bitstream Protection -- Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture
Dimensions
unknown
Extent
1 online resource (XIV, 346 p.)
File format
multiple file formats
Form of item
online
Isbn
9783540786108
Level of compression
uncompressed
Media category
computer
Media type code
c
Other control number
10.1007/978-3-540-78610-8
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
  • (CKB)1000000000490913
  • (SSID)ssj0000319781
  • (PQKBManifestationID)11265298
  • (PQKBTitleCode)TC0000319781
  • (PQKBWorkID)10343376
  • (PQKB)10169609
  • (DE-He213)978-3-540-78610-8
  • (MiAaPQ)EBC3063621
  • (EXLCZ)991000000000490913
Label
Reconfigurable Computing: Architectures, Tools and Applications : 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings, edited by Roger Woods, Katherine Compton, Christos Bouganis, Pedro C. Diniz, (electronic resource)
Publication
Note
Bibliographic Level Mode of Issuance: Monograph
Antecedent source
mixed
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
cr
Color
not applicable
Content category
text
Content type code
txt
Contents
Keynotes -- Synthesizing FPGA Circuits from Parallel Programs -- From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing -- The von Neumann Syndrome and the CS Education Dilemma -- Programming and Compilation -- Optimal Unroll Factor for Reconfigurable Architectures -- Programming Reconfigurable Decoupled Application Control Accelerator for Mobile Systems -- DNA and String Processing Applications -- DNA Physical Mapping on a Reconfigurable Platform -- Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension -- Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs -- Scientific Applications -- A Custom Processor for a TDMA Solver in a CFD Application -- A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation -- Reconfigurable Computing Hardware and Systems -- Physical Design of FPGA Interconnect to Prevent Information Leakage -- Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs -- Run-Time Adaptable Architectures for Heterogeneous Behavior Embedded Systems -- Image Processing -- FPGA-Based Real-Time Super-Resolution on an Adaptive Image Sensor -- A Parallel Hardware Architecture for Image Feature Detection -- Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System -- Run-Time Behavior -- A New Self-managing Hardware Design Approach for FPGA-Based Reconfigurable Systems -- A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor -- Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens -- Instruction Set Extension -- ARISE Machines: Extending Processors with Hybrid Accelerators -- The Instruction-Set Extension Problem: A Survey -- Random Number Generation and Financial Computation -- An FPGA Run-Time Parameterisable Log-Normal Random Number Generator -- Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA -- Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models -- Posters -- Hybrid-Mode Floating-Point FPGA CORDIC Co-processor -- Multiplier-Based Double Precision Floating Point Divider According to the IEEE-754 Standard -- Creating the World’s Largest Reconfigurable Supercomputing System Based on the Scalable SGI® Altix® 4700 System Infrastructure and Benchmarking Life-Science Applications -- Highly Efficient Structure of 64-Bit Exponential Function Implemented in FPGAs -- A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures -- PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications -- Stream Transfer Balancing Scheme Utilizing Multi-path Routing in Networks on Chip -- Efficiency of Dynamic Reconfigurable Datapath Extensions – A Case Study -- Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices -- Data Reallocation by Exploiting FPGA Configuration Mechanisms -- A Networked, Lightweight and Partially Reconfigurable Platform -- Neuromolecularware – A Bio-inspired Evolvable Hardware and Its Application to Medical Diagnosis -- An FPGA Configuration Scheme for Bitstream Protection -- Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture
Dimensions
unknown
Extent
1 online resource (XIV, 346 p.)
File format
multiple file formats
Form of item
online
Isbn
9783540786108
Level of compression
uncompressed
Media category
computer
Media type code
c
Other control number
10.1007/978-3-540-78610-8
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
  • (CKB)1000000000490913
  • (SSID)ssj0000319781
  • (PQKBManifestationID)11265298
  • (PQKBTitleCode)TC0000319781
  • (PQKBWorkID)10343376
  • (PQKB)10169609
  • (DE-He213)978-3-540-78610-8
  • (MiAaPQ)EBC3063621
  • (EXLCZ)991000000000490913

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