The Resource Tools for High Performance Computing 2011 : Proceedings of the 5th International Workshop on Parallel Tools for High Performance Computing, September 2011, ZIH, Dresden, edited by Holger Brunst, Matthias S. Müller, Wolfgang E. Nagel, Michael M. Resch, (electronic resource)

Tools for High Performance Computing 2011 : Proceedings of the 5th International Workshop on Parallel Tools for High Performance Computing, September 2011, ZIH, Dresden, edited by Holger Brunst, Matthias S. Müller, Wolfgang E. Nagel, Michael M. Resch, (electronic resource)

Label
Tools for High Performance Computing 2011 : Proceedings of the 5th International Workshop on Parallel Tools for High Performance Computing, September 2011, ZIH, Dresden
Title
Tools for High Performance Computing 2011
Title remainder
Proceedings of the 5th International Workshop on Parallel Tools for High Performance Computing, September 2011, ZIH, Dresden
Statement of responsibility
edited by Holger Brunst, Matthias S. Müller, Wolfgang E. Nagel, Michael M. Resch
Creator
Contributor
Editor
Editor
Subject
Language
  • eng
  • eng
Summary
The proceedings of the 5th International Workshop on Parallel Tools for High Performance Computing provide an overview on supportive software tools and environments in the fields of System Management, Parallel Debugging and Performance Analysis. In the pursuit to maintain exponential growth for the performance of high performance computers the HPC community is currently targeting Exascale Systems. The initial planning for Exascale already started when the first Petaflop system was delivered. Many challenges need to be addressed to reach the necessary performance. Scalability, energy efficiency and fault-tolerance need to be increased by orders of magnitude. The goal can only be achieved when advanced hardware is combined with a suitable software stack. In fact, the importance of software is rapidly growing. As a result, many international projects focus on the necessary software
Dewey number
  • 004
  • 004.24
  • 004.3
  • 005.1
http://bibfra.me/vocab/relation/httpidlocgovvocabularyrelatorsedt
  • 9hag_-qR4P0
  • ivJjcOvMmNQ
  • 4X_EsY_sYac
  • y_TEfhcpemw
Language note
English
LC call number
QA76.9.E94
Literary form
non fiction
http://bibfra.me/vocab/lite/meetingDate
2011
http://bibfra.me/vocab/lite/meetingName
International Workshop on Parallel Tools for High Performance Computing
Nature of contents
dictionaries
http://library.link/vocab/relatedWorkOrContributorName
  • Brunst, Holger.
  • Müller, Matthias S.
  • Nagel, Wolfgang E.
  • Resch, Michael M.
http://library.link/vocab/subjectName
  • Computer system performance
  • Operating systems (Computers)
  • Computer science
  • Computer software
  • Data mining
  • System Performance and Evaluation
  • Performance and Reliability
  • Programming Languages, Compilers, Interpreters
  • Algorithm Analysis and Problem Complexity
  • Data Mining and Knowledge Discovery
  • Computer Applications
Label
Tools for High Performance Computing 2011 : Proceedings of the 5th International Workshop on Parallel Tools for High Performance Computing, September 2011, ZIH, Dresden, edited by Holger Brunst, Matthias S. Müller, Wolfgang E. Nagel, Michael M. Resch, (electronic resource)
Instantiates
Publication
Note
Description based upon print version of record
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
  • cr
Content category
text
Content type code
  • txt
Contents
  • ""Tools for High Performance Computing 2011 ""; ""Preface""; ""Contents""; ""Contributors""; ""Chapter 1 Creating a Tool Set for Optimizing Topology-Aware Node Mappings ""; ""1.1 Motivation and Background""; ""1.2 Gaining Insight from Multiple Perspectives""; ""1.2.1 The HAC Model""; ""1.2.2 Domains Relevant for Node Mappings""; ""1.2.3 Mapping Communication to Hardware Data""; ""1.3 Creating a Flexible Measurement Environment""; ""1.3.1 Concurrent Measurements Using PNMPI""; ""1.3.2 Gathering Data in the Hardware Domain""; ""1.3.3 Gathering Data in the Communication Domain""
  • ""1.3.4 Phase Attribution""""1.3.5 Data Storage in Structured YAML Files""; ""1.3.6 Investigating Best Case Mappings""; ""1.3.7 Approximating Collectives""; ""1.4 Preliminary Results""; ""1.5 Related Work""; ""1.6 Conclusions and Future Work""; ""References""; ""Chapter 2 Using Sampling to Understand Parallel Program Performance ""; ""2.1 Introduction""; ""2.2 Call Path Profiling""; ""2.3 Pinpointing Scaling Bottlenecks""; ""2.4 Blame Shifting""; ""2.4.1 Parallel Idleness and Overhead in Work Stealing""; ""2.4.2 Lock Contention""; ""2.4.3 Load Imbalance""; ""2.5 Call Path Tracing""
  • ""2.6 Data-Centric Performance Analysis""""2.7 Conclusions""; ""References""; ""Chapter 3 likwid-bench: An Extensible Microbenchmarking Platform for x86 Multicore Compute Nodes ""; ""3.1 Introduction""; ""3.2 Related Work""; ""3.3 Architecture""; ""3.4 Benchmark .ptt File Format""; ""3.5 Command Line Syntax""; ""3.6 Examples""; ""3.6.1 Identifying Bandwidth Bottlenecks""; ""3.6.2 Characterizing ccNUMA Properties""; ""3.7 Conclusion and Outlook""; ""References""; ""Chapter 4 An Open-Source Tool-Chain for Performance Analysis ""; ""4.1 Introduction""; ""4.2 Related Work""
  • ""4.3 Instrumenting Applications with EZTrace""""4.3.1 Tracing the Execution of an Application""; ""4.3.2 Instrumenting an Application""; ""4.4 Creating Trace Files with GTG ""; ""4.4.1 Overview of GTG""; ""4.4.2 Interaction Between GTG and EZTrace""; ""4.5 Analyzing Trace Files with ViTE""; ""4.5.1 A Generic Trace Visualizer""; ""4.5.2 Displaying Millions of Events""; ""4.6 Evaluation""; ""4.6.1 Overhead of Trace Collection""; ""4.6.2 NAS Parallel Benchmarks""; ""4.7 Conclusion and Future Work""; ""References""; ""Chapter 5 Debugging CUDA Accelerated Parallel Applications with TotalView ""
  • ""5.1 Introduction""""5.1.1 HPC Debugging Challenges""; ""5.1.2 CUDA and Heterogeneous Acceleration Architectures""; ""5.1.3 Challenges Introduced by CUDA""; ""5.1.4 The TotalView Debugger""; ""5.2 TotalView for CUDA""; ""5.2.1 Previous Experience: Cell""; ""5.2.2 The NVIDIA GPU Architecture and CUDA""; ""5.2.3 The TotalView Model: Extended for CUDA""; ""5.2.4 Challenges and Features""; ""5.2.4.1 Extending the Thread Model""; ""5.2.4.2 Dealing with Different Memory Spaces""; ""5.2.4.3 Dealing with Inlined Functions""; ""5.2.4.4 Thread Control and Single Stepping the GPU""
  • ""5.2.4.5 CUDA Memory Exceptions""
Dimensions
unknown
Edition
1st ed. 2012.
Extent
1 online resource (165 p.)
Form of item
online
Isbn
9781283640596
Media category
computer
Media type code
  • c
Other control number
10.1007/978-3-642-31476-6
Specific material designation
remote
System control number
  • (CKB)2670000000535904
  • (EBL)994569
  • (OCoLC)811563986
  • (SSID)ssj0000767609
  • (PQKBManifestationID)11941726
  • (PQKBTitleCode)TC0000767609
  • (PQKBWorkID)10741352
  • (PQKB)10063780
  • (DE-He213)978-3-642-31476-6
  • (MiAaPQ)EBC994569
  • (EXLCZ)992670000000535904
Label
Tools for High Performance Computing 2011 : Proceedings of the 5th International Workshop on Parallel Tools for High Performance Computing, September 2011, ZIH, Dresden, edited by Holger Brunst, Matthias S. Müller, Wolfgang E. Nagel, Michael M. Resch, (electronic resource)
Publication
Note
Description based upon print version of record
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
  • cr
Content category
text
Content type code
  • txt
Contents
  • ""Tools for High Performance Computing 2011 ""; ""Preface""; ""Contents""; ""Contributors""; ""Chapter 1 Creating a Tool Set for Optimizing Topology-Aware Node Mappings ""; ""1.1 Motivation and Background""; ""1.2 Gaining Insight from Multiple Perspectives""; ""1.2.1 The HAC Model""; ""1.2.2 Domains Relevant for Node Mappings""; ""1.2.3 Mapping Communication to Hardware Data""; ""1.3 Creating a Flexible Measurement Environment""; ""1.3.1 Concurrent Measurements Using PNMPI""; ""1.3.2 Gathering Data in the Hardware Domain""; ""1.3.3 Gathering Data in the Communication Domain""
  • ""1.3.4 Phase Attribution""""1.3.5 Data Storage in Structured YAML Files""; ""1.3.6 Investigating Best Case Mappings""; ""1.3.7 Approximating Collectives""; ""1.4 Preliminary Results""; ""1.5 Related Work""; ""1.6 Conclusions and Future Work""; ""References""; ""Chapter 2 Using Sampling to Understand Parallel Program Performance ""; ""2.1 Introduction""; ""2.2 Call Path Profiling""; ""2.3 Pinpointing Scaling Bottlenecks""; ""2.4 Blame Shifting""; ""2.4.1 Parallel Idleness and Overhead in Work Stealing""; ""2.4.2 Lock Contention""; ""2.4.3 Load Imbalance""; ""2.5 Call Path Tracing""
  • ""2.6 Data-Centric Performance Analysis""""2.7 Conclusions""; ""References""; ""Chapter 3 likwid-bench: An Extensible Microbenchmarking Platform for x86 Multicore Compute Nodes ""; ""3.1 Introduction""; ""3.2 Related Work""; ""3.3 Architecture""; ""3.4 Benchmark .ptt File Format""; ""3.5 Command Line Syntax""; ""3.6 Examples""; ""3.6.1 Identifying Bandwidth Bottlenecks""; ""3.6.2 Characterizing ccNUMA Properties""; ""3.7 Conclusion and Outlook""; ""References""; ""Chapter 4 An Open-Source Tool-Chain for Performance Analysis ""; ""4.1 Introduction""; ""4.2 Related Work""
  • ""4.3 Instrumenting Applications with EZTrace""""4.3.1 Tracing the Execution of an Application""; ""4.3.2 Instrumenting an Application""; ""4.4 Creating Trace Files with GTG ""; ""4.4.1 Overview of GTG""; ""4.4.2 Interaction Between GTG and EZTrace""; ""4.5 Analyzing Trace Files with ViTE""; ""4.5.1 A Generic Trace Visualizer""; ""4.5.2 Displaying Millions of Events""; ""4.6 Evaluation""; ""4.6.1 Overhead of Trace Collection""; ""4.6.2 NAS Parallel Benchmarks""; ""4.7 Conclusion and Future Work""; ""References""; ""Chapter 5 Debugging CUDA Accelerated Parallel Applications with TotalView ""
  • ""5.1 Introduction""""5.1.1 HPC Debugging Challenges""; ""5.1.2 CUDA and Heterogeneous Acceleration Architectures""; ""5.1.3 Challenges Introduced by CUDA""; ""5.1.4 The TotalView Debugger""; ""5.2 TotalView for CUDA""; ""5.2.1 Previous Experience: Cell""; ""5.2.2 The NVIDIA GPU Architecture and CUDA""; ""5.2.3 The TotalView Model: Extended for CUDA""; ""5.2.4 Challenges and Features""; ""5.2.4.1 Extending the Thread Model""; ""5.2.4.2 Dealing with Different Memory Spaces""; ""5.2.4.3 Dealing with Inlined Functions""; ""5.2.4.4 Thread Control and Single Stepping the GPU""
  • ""5.2.4.5 CUDA Memory Exceptions""
Dimensions
unknown
Edition
1st ed. 2012.
Extent
1 online resource (165 p.)
Form of item
online
Isbn
9781283640596
Media category
computer
Media type code
  • c
Other control number
10.1007/978-3-642-31476-6
Specific material designation
remote
System control number
  • (CKB)2670000000535904
  • (EBL)994569
  • (OCoLC)811563986
  • (SSID)ssj0000767609
  • (PQKBManifestationID)11941726
  • (PQKBTitleCode)TC0000767609
  • (PQKBWorkID)10741352
  • (PQKB)10063780
  • (DE-He213)978-3-642-31476-6
  • (MiAaPQ)EBC994569
  • (EXLCZ)992670000000535904

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